1. Field of the Invention
The present invention relates to output buffers with circuitry to increase operation speed. More particularly, the present invention relates to output buffers for high density programmable logic devices (PLDs).
2. Description of the Related Art
FIG. 1 shows a block diagram for a typical high density PLD such as the MACH130 manufactured by Advanced Micro Devices, Inc. As shown, the high density PLD includes four programmable array logic (PAL) blocks 101-104 interconnected by a programmable switch matrix 106. The PAL blocks 101-104 can be viewed as independent PLD devices on the chip, each similar to the popular lower density 22V10 PAL device, also available from Advanced Micro Devices, Inc. The switch matrix 106 connects the PAL blocks to each other and to all I/O pins 111-114 enabling a device, such as the MACH130, to provide six times the logic capability of the 22V10.
FIG. 2 shows greater detail for one quarter of the PLD block diagram of FIG. 1, including PAL block 101 as connected to switch matrix 106. Note that circuit components, such as switch matrix 106 carried forward from FIG. 1 are similarly labeled in FIG. 2, as will be circuit components carried forward in subsequent figures. PAL block 101 receives inputs, such as the 26 inputs shown, from the switch matrix 106 in input buffers 202. Input buffers 202 buffer the signals to AND array and logic allocator circuitry 204 which provides programmable AND and OR logic between the input buffers 202 and output logic macrocells 206.
The output logic macrocells 206 are programmable to provide registered or combinatorial outputs. The outputs of the macrocells 206 are provided to tri-state output buffers 208 and are also provided on feedback lines to the switch matrix 106.
Each tri-state output buffer 208 can be enabled for use as an output buffer, or disabled so that I/O ports 111 can provide input signals to the PLD. Enabling or disabling signals for the tri-state buffers are provided by the AND array and logic allocator circuit 204. When the tri-state output buffers 208 are enabled, outputs are provided from the output buffers 208 through I/O ports 111 as well as through feedback lines to the switch matrix 106. When the output buffers 208 are disabled, input signals from external circuitry are provided through I/O ports 111 to the switch matrix 106. The switch matrix 106 includes circuitry to distribute the signals received from the tri-state output buffers 208, I/O ports 111 and macrocells 206 back to the PAL blocks 101-104.
Circuitry for output buffers of a high density PLD can be configured to provide more speed than a low density PLD such as the 22V10. A low density PLD is typically provided in a package with only one ground pin connection, but a high density PLD is typically provided in a larger package with multiple ground pins. With a limited number of ground pins, the lower density PLDs typically experience more ground bounce noise, limiting the speed at which the output buffers can switch in comparison to output buffers for high density PLDs.
FIG. 3 shows conventional circuitry for a buffer 300 which may be configured with enabling/disabling circuitry for use as one of the tri-state buffers 208 of FIG. 2. The buffer 300 receives a data signal DOUT, such as an output of one of macrocells 206 of FIG. 2, at its input and provides an output signal OUT at its output to external circuitry on a line such as one of I/O ports 111 of FIG. 2. The DOUT signal is provided along a first path through two series inverters 306 and 308 to the gate of a pull up transistor 302. The DOUT signal is provided along a second path through a single inverter 310 to the gate of a pull down transistor 304. Inverters 306, 308 and 310 include a p-channel pull up transistor and an n-channel pull down transistor. The output signal OUT is pulled up to V.sub.DD by the pull up transistor 302. The output signal OUT is pulled down to V.sub.SS by the pull down transistor 304. The circles on transistors, such as the pull up transistors of inverters 306, 308 and 310, indicate a p-channel transistor, while transistors without the circles are n-channel transistors.
The circuitry of FIG. 3 has several disadvantages. First, by using two inverters 306 and 308 to drive the pull up transistor 302 and one inverter 310 to drive pull down transistor 304, the additional inverter driving the pull up transistor 302 can cause added delay resulting in transistors 302 and 304 being turned on together for an extended time period (i.e. crowbar).
Additionally, because the p-channel transistors of inverters 306, 308 and 310 have 1/2 to 1/3 the drive capability of the same size n-channel transistor due to lower mobility, the p-channel transistors must be larger, thus loading the input of the buffer 300. Additionally, with p-channel transistors, Miller effect parasitic capacitance is greater due to the larger transistor size. The Miller effect capacitance adds in series with parasitic drain capacitance, further increasing loading of the input of buffer 300.